With the continuous development of semiconductor technology, the technical node of semiconductor devices has become smaller and smaller. However, due to the resolution limitation of the existing photolithography processes, the features formed by the existing photolithography processes are unable to match the requirements for continuously reducing the critical dimension (CD) of the semiconductor devices. Therefore, further development of the semiconductor technology may be restrained.
In order to further reduce the CD of the semiconductor devices based on the existing photolithography process, various double patterning processes have been developed. Amongst of the double patterning processes, the Self-Aligned Double Patterning (SADP) process has been widely used because the SADP process is relatively simple.
FIGS. 1˜3 illustrate structures corresponding to certain stages of an existing double patterning process. As shown in FIG. 1, the process includes providing a substrate 100. The substrate 100 is subsequently etched to form desired features. A sacrificial layer 101 is formed on the surface of the substrate 100. The sacrificial layer 101 is formed by a photolithography process.
Further, as shown in FIG. 2, sidewalls 103a are formed on the surface of the substrate 100 at both sides of the sacrificial layer 101. That is, the sidewalls 103 are formed on the side surfaces of the sacrificial layer 101.
Further, as shown in FIG. 3, after forming the sidewalls 103a, the sacrificial layer 101 is removed. Thus, the independent sidewalls 103a are formed.
Further, after removing the sacrificial layer 101, the substrate 100 is etched using the independent sidewalls 103a as an etching mask. Thus, patterned features are formed on substrate 100; and such a process is referred as a double patterning process.
However, the morphology of the sidewalls 103a may be unable to match the desired requirements. Thus, the morphology of the patterned features formed by using the sidewalls 103a as an etching mask may also be unable to match the desired requirements. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.